Production scheduling secrets used by semiconductor factories｜Process + Algorithm explained in one go

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Semiconductor manufacturing involves complex features such as multi-layer structures, long processes, multiple entries, strict time windows (Q-Time), and differences in equipment capabilities. It is one of the most difficult scenarios to schedule in the discrete manufacturing industry. A typical 8-inch/12-inch Fab usually has hundreds of process equipment and thousands of processes. The number of steps a single wafer goes through from wafer production to shipment can reach 600~1,000. The overall scheduling problem is extremely high-dimensional.

This article combines the terminology system in "Concept Notes Related to Semiconductor Scheduling", starting from the basic concepts, and systematically introduces the main processes, typical algorithms and representative cases of semiconductor production scheduling.

Total text: 6337 words

Estimated reading time: 15 minutes

1. Basic core concepts of the industry

1

Materials and equipment terminology

• Wafer:The smallest physical carrier for semiconductor processing, semiconductor production is settled in Wafer units.

• Lot:A full lot usually carries 25 pieces of wafer; in most processes, the 25 pieces inside the lot need to be processed continuously and cannot be split into batches.

• EQP (machine/equipment):The physical equipment that performs processing actions is the core resource for scheduling decisions.

• Capability:The set of process types that the machine can perform determines which steps the machine can undertake.

• Recipe:A set of process parameters (temperature, gas, time, etc.) used when executing a specific Step on a specified machine. The same Capability usually corresponds to multiple Recipes.

• Move： The shipment volume measured in Wafer units is the core KPI for measuring machine/production line production capacity and execution, and is usually measured along the EQP × Capability dimension.

2

Process positioning concept (Where am I)

Since the chip has a multi-layer structure, each layer needs to perform glue coating, photolithography, development, etching, deposition, CMP and other steps in sequence, and there are multiple entries (the same wafer goes to the same machine on different layers), so a variety of positioning concepts with different granularities are required:

• Step： The actual process step of the current Wafer is the most granular positioning of RTD/RTS.

• Layer： The physical layer of semiconductor processing.

• Stage： Factory-defined processing stages (coarse-grained), often used for production capacity accounting and KPI statistics.

• Loop： A factory-defined process step queue segment often corresponds to a group of processes that are physically to be completed continuously.

A product corresponds to a complete list of Steps (route), and each Step requires Lot to be processed on a machine with specific capabilities.

3

Key Parameters in RTD Decision-Making

• Move (planned delivery quantity):Usually defined on EQP × Capability, it is the output target of RTD decision-making.

• WIP (work in progress):The number of wafers currently being/will be processed by the machine; used both as algorithm input (describing the initial state) and as auxiliary variables (controlling the upper limit to avoid buffer overflow).

• Buffer： The material buffer zone before and after the machine is limited by physical space and needs to be strictly constrained during scheduling.

4

Q-Time and Q-Zone

Since semiconductor production involves factors such as chemical coatings such as photoresist and heat treatment, after processing is completed, the next process must be entered within a limited time, otherwise yield accidents such as chemical reaction deactivation and surface oxidation will occur. This type of time window constraints are collectively called Q-Time:

• Max Q-Time： The maximum allowable interval from the end of the previous process to the start of the next process.

• Min Q-Time： The minimum waiting time required for stable conditions (such as cooling after heat treatment).

• Q-Zone： Several consecutive processes must be completed within Q-Time to form a time window interval. Delays in any process within the Q-Zone can result in the entire section being scrapped.

Q-Time/Q-Zone is the most important constraint that distinguishes semiconductor scheduling from the general Job Shop, and is also the main source of the complexity explosion of scheduling algorithms.

2. Main processes of production scheduling

1

Two-tier architecture of APS and RTS

The planning and scheduling system of a semiconductor factory is usually divided into two layers: the macro layer APS (Advanced Planning and Scheduling) for long-term planning, and the micro layer RTS/RTD (Real Time Scheduling/Real Time Dispatching) for real-time dispatch. The two are independent and interconnected, and together determine the operating efficiency of the Fab.

2

APS long-term planning main process

1. Collect CDP (Customer Demand Planning):Summarize customer demand plans to form a product/quantity/delivery demand pool.

2. Establish basic data on process and production capacity:Import product Route, Capability, machine capacity, downtime/maintenance plan, and current WIP snapshot.

3. Capacity accounting (Loading Plan):Project the candidate MPS onto each Capability to obtain the weekly/monthly Loading curve to determine bottlenecks.

4. Film production plan optimization:With profit/delivery/inventory as the goal, the weekly wafer production volume of each product is calculated under the constraints of the upper limit of production capacity.

5. Equipment investment optimization:When the existing production capacity cannot meet the CDP, the optimal machine entry plan and time point will be deduced.

6. Export MPS, WS, WO plans:Solidify it into an executable target for the underlying RTS/MES system, and update it on a rolling basis on a regular basis.

3

RTS/RTD real-time scheduling main process

1. Real-time data collection:Obtain the current WIP, machine status (idle/down/busy), Reticle presence, Q-Time remaining, and Buffer water level from MES.

2. Candidate Lot-EQP matches:Based on the Step→Capability→EQP mapping, all executable (Lot, EQP, Recipe) triples are generated.

3. Constraint pruning:Eliminate candidates that violate Q-Time, Buffer, Reticle, and maintenance windows.

4. Objective function score:Weighted scoring is made based on Move goal, Cycle Time, Key Lot priority, Recipe/Reticle switching loss, etc.

5. Work dispatch decision-making and release:Select the Top candidates, generate work dispatch orders and write back to MES; additionally output schedules for several hours in the future for key processes such as furnace tubes/lithography.

6. Event driven reordering:In the event of equipment failure, emergency Lot, or Q-Time is about to exceed the limit, incremental recalculation is triggered to keep the schedule executable.

3. Core algorithm

Mathematical Programming (LP/MILP):

Use mixed integer linear programming to model long-term problems: the decision variables are the production volume and machine loading of each week/product, and the objective function is maximizing profit or weighted delivery satisfaction rate. Common constraints: Cumulative Loading per Capability week ≤ available capacity, output of each product ≥ customer demand, WIP balance. Solvers generally use Gurobi, CPLEX, COPT, OR-Tools. The advantage is global optimality and strong interpretability; the disadvantage is that the solution time is uncontrollable at a large scale and requires techniques such as column generation, Benders decomposition, and rolling time windows.

Dispatching Rules:

The most commonly used in RTS, extremely fast and easy to interpret, representative methods: FIFO, SPT (Shortest Processing Time), EDD (Earliest Due Date), Critical Ratio (CR), Least Slack, ODD (Operation Due Date), Hotlot Priority, etc. Actual systems often combine multiple rules into a weighted scoring function, and combine Q-Time residuals, Key Lot flags, and Reticle in-place status for fusion and sorting.

Constraint programming (CP):

Constraint programming is good at describing combination constraints such as time windows, sequences, and mutual exclusions, and is especially suitable for scenarios such as Q-Zone, furnace tube batch combination, and Reticle mutual exclusion. Commonly used tools: Google OR-Tools CP-SAT, IBM CP Optimizer. The modeling is flexible and feasible solutions can be obtained quickly. With Large Neighborhood Search (LNS), medium-sized problems can be solved in tens of seconds.

Metaheuristics:

For large-scale combinatorial optimization of medium and long-term scheduling, genetic algorithms (GA), simulated annealing (SA), tabu search (TS), particle swarm (PSO) and their hybrid algorithms are commonly used. They use feasible solutions as a population, explore the solution space through neighborhood search/evolution operators, and are suitable for problems such as furnace tube batch combination and photolithography daily scheduling. The advantage is that it is scalable and can provide high-quality solutions within a limited time; the disadvantage is that the solution is unstable and is often used in conjunction with heuristic initialization and CP local repair in engineering.

Simulation + Optimization (DES + Optimization):

Use discrete event simulation (DES) to model the entire plant or section, put candidate labor dispatch strategies into the simulator for evaluation, and combine black box optimization methods such as Bayesian optimization and CMA-ES for optimization. Commonly used in the production of simulation products, capacity verification, and What-If analysis; it is also a standard method for verifying RTD rule parameters.

Reinforcement Learning and AI Agent:

Model the work dispatch decision as a Markov decision-making process (status = WIP/machine/Q-Time remaining, action = which Lot to choose, reward = Move/delivery/yield rate), and train the policy network through algorithms such as DQN and PPO. AI large model agents are used for data governance and SOP automation: natural language analysis alarms, automatic generation of cleaning scripts, and assisted anomaly root cause analysis.

Sub-product and algorithm selection comparison:

4. Introduction to typical cases

1

Dynamic dispatch of work in the photolithography area (RTS + Reticle

constraint)

Scenario:There are 8 Scanners in a certain 12-inch Fab lithography area. Each Scanner supports limited Recipes, and the corresponding Reticle can only be loaded on one machine at a time. Reticle switching takes about 15 to 30 minutes, which is the largest hidden capacity loss in this area.

Modeling:State variables include the current Reticle, Lot queue, and Q-Time remaining of each machine; constraints include mutual exclusion of the same Reticle, machine Capability, and Q-Time upper limit; goal: maximize Move + minimize the number of switching times.

Algorithm:The heuristic rule of Critical Ratio + Reticle on-site bonus points is used to dispatch workers in real time, rolling every 5 minutes. At the same time, CP-SAT is used to solve the preview of the next 8 hours as a reference for dispatching scores.

Effect:The number of reticle switching is reduced by about 30%, the effective moves in the photolithography area are increased by 6~8%, and the cycle time is shortened by about 4%.

2

Furnace Tube Batch Scheduling

Scenario:Furnace is used for long-term high-temperature processing (oxidation, annealing, LPCVD, etc.). It can load 4~6 Lots at a time to form a Boat, and the processing time is 4~10 hours. Improper batch combination will result in double waste of waiting batches and scattered batches.

Modeling:Decisions include "which Lots form the same Boat", "which furnace tube" and "when to start". Constraints include recipe compatibility, temperature mutual exclusion, Q-Time, future arrival lot prediction, and maintenance windows.

Algorithm:CP-SAT describes batch combination + sorting constraints, genetic algorithm performs combination space exploration, and simulation performs full load rate and waiting time evaluation.

Effect:The full load rate is increased from 78% to 91%, and the cycle time of the furnace tube area is shortened by more than 12%.

3

Continuous Q-Time / Q-Zone Scheduling

Scenario:The cleaning-deposition-annealing section of a certain high-end logic process constitutes a Q-Zone, and the entire process must be completed within 6 hours, otherwise it needs to be reworked or scrapped; there are also multiple entries in this section.

Modeling:Q-Zone is abstracted into a serial subgraph with a hard time window; for multiple entries, a layer-by-layer step sequence is introduced to distinguish the process differences between different layers of the same machine.

Algorithm:CP + Large Neighborhood Search obtains the initial plan; after entering the execution stage, the remaining Q-Time is used as the highest priority dispatch scoring item; when it is predicted that a Lot will time out, the time window rescue strategy is triggered: seize the bottleneck machine or fall back to the previous buffer.

Effect:Q-Time default rates dropped by approximately 75%, and rework/scrap wafers due to Q-Time were significantly reduced.

4

MTO Production Plan (APS)

Scenario:The customer provides a CDP for the next 13 weeks, which needs to maximize profits while meeting key order delivery deadlines and be compatible with the current WIP.

Modeling:The decision variable is the production volume of each product in each week; the constraint is the cumulative Loading of each Capability week ≤ available production capacity, considering the yield, considering the existing WIP promotion; the target is the weighted profit minus the delivery delay penalty.

Algorithm:Rolling time window MILP (rolling weekly) + solver (Gurobi / COPT), and interactive What-If analysis with Excel template.

Effect:The accurate delivery rate of key orders increased from 86% to 96%, and monthly profits increased by 3~5%.

5

MTS safety stock production

Scenario:Maintaining the lower limit of safety stock for standard products based on market forecasts requires a balance between inventory turnover and capacity utilization.

Modeling:Use the (s, S) inventory strategy to trigger production orders, and allocate orders to production lines based on production capacity accounting; use CVaR or robust optimization to handle forecast uncertainty.

Algorithm:Random/robust MILP + periodic rolling generation plan, and automatically release the order to RTS.

Effect:Safety stock out-of-stock incidents have been reduced by approximately 60%, and machine utilization rate fluctuations have been narrowed by approximately 35%.

6

Key Lot full-process circulation plan

Scenario:A small number of key lots of strategic customers require green channels to shorten cycle time as much as possible without seriously affecting ordinary lots.

Modeling:Abstract the remaining Route of the Key Lot into a shortest path problem, with each edge corresponding to an executable machine + expected waiting time; increase the weight of the Key Lot in the dispatch scoring function.

Algorithm:Path pre-arrangement (CP + Dijkstra variant) + dispatch score weighting + simulation verification of the disturbance amplitude to ordinary Lots.

Effect:Key Lot Cycle Time is shortened by 20%~30%, and the negative impact on the overall Cycle Time is controlled within 2%.

5. Summary

The core of semiconductor production scheduling is: macroscopically, APS is used for long-term production capacity and wafer production planning, and microscopically, RTS/RTD is used for real-time labor dispatch and time window guarantee. The two layers are coupled through common languages ​​such as MPS, WIP, and Loading. In terms of algorithm selection, long periods favor mathematical programming and robust optimization, while short periods favor scheduling rules, constraint programming and metaheuristics, supplemented by simulation and AI for parameter optimization and exception handling. Sub-products such as Planning, Furnace Tube, Photolithography, Key Lot, Continuous Q-Time, Production Simulation, and Data Management, which are designed around the unique constraints of semiconductors such as Q-Time, Reticle, Buffer, and multiple entries, form a complete APS product matrix.

In engineering practice, "algorithm + real-time data + business rules" are indispensable. Only by deeply integrating domain knowledge into algorithm modeling can we continue to generate value in the complex and changing scenarios of real Fab.

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Machine-translated from the Chinese original 半导体厂都在用的排产秘籍｜流程 + 算法一次讲透 (published 2025-06-18). WeChat original ↗